1. Field of the Invention
The present invention relates to integrated circuits on semiconductor substrates, and more particularly to the fabrication of ohmic contacts relating to Thin Film Transistors (TFT) on Static Random Access Memory (SRAM).
2. Description of the Prior Art
Random Access Memory (RAM) is used extensively in the electronics industry for storing data for digital systems, such as computers. The major types of RAMs, are the Dynamic Random Access Memory (DRAM) and the Static Random Access Memory (SRAM). The individual DRAM cells, composed of a single transistor and capacitor store information on the capacitors as charge. In general the DRAM is slower than the SRAM and needs to be refreshed periodically to maintain the charge on the capacitor, but is considerably cheaper to produce per bit of information stored than the SRAM. The SRAM cell, on the other hand, is usually composed of six transistors and functions as a static latch or flip flop circuit, does not have to be refreshed and is much faster than the DRAM. Because of its speed the SRAM is ideal for use as a cache or buffer memory to speed up the system performance.
A circuit schematic for a typical six-transistor CMOS SRAM cell is shown in FIG. 1. Only one of the array of many cells is shown in FIG. 1. The trend in recent years is to fabricate the CMOS SRAMs using a P channel Thin Film Transistor (TFT) for the P1 and P2 transistors to reduce the size of the cell and the cost of the chip. For example, T. Okazawa, U.S. Pat. No. 4,980,732 teaches a method for making TFTs with lower off currents. In that patent the FET drain side of channel is off set from the gate electrode to reduce the current. Briefly, the SRAM cell functions as follows. Referring to FIG. 1, an applied gate voltage on the word line WL switch on the pass transistors WN1 and WN2. The voltage at the nodes Q1 and Q2 between the two pairs of CMOS transistor P1, N1 and P2, N2, are sensed on the bit lines BL1 and BL2 during the read cycle to determine the state of the SRAM latch. During the write cycle an impressed voltage on the bit lines can switch the voltage levels on the latch and thereby change the stored binary data representing one's and zero's.
However, during fabrication of the SRAM cell the nodes Q1 and Q2 between each pair of CMOS P-channel and N-channel FETs must, respectively, make good electrical contact to the gate electrodes G2 and G1, as shown in the circuit schematic of FIG. 1. Unfortunately, when the P-channel TFT are built on the semiconductor substrate by methods of the prior art, a number of additional processing problems occur that limit the performance and reliability of the SRAM.
These problems are best understood by referring to the conventional prior art process for forming the P-type TFT, as shown in schematic cross-sectional views in FIGS. 2 through 5. In order to simplify the discussion only portions of the substrate for the SRAM cell is shown on which the P-channel TFT is built. The other circuit elements, such as the WN1, WN2 FETs and the word line formed from a first polysilicon layer and the bit lines formed from a second polysilicon layer are not shown in FIGS. 2 through 5.
After completing portions of the word line and bit line structure on substrate 10, the latch circuits of the SRAM memory cells are formed having the P-channel TFTs on portions of the substrate within the array of word and bit lines. Referring now to FIG. 2, the TFT gate electrodes G1 and G2 are patterned from an N.sup.+ doped third polysilicon layer 14. A thin gate oxide 16 is then deposited over the gate electrodes, also shown in FIG. 2. A contact opening 2 is then formed in the gate oxide to the second gate G2 (see FIG. 3) by photoresist masking and etching. A fourth polysilicon layer 18 is then deposited and patterned to form the TFT channel layer 18 over the G1 gate electrode and makes contact to the G2 gate electrode in opening 2, as shown in FIG. 4. The layer 18 is then implanted with a P-type dopant through a patterned photoresist mask to form the source and drain areas of the P-channel TFT and at the same time forming an electrical connection from the drain 20 of the TFT, which is also the node point Q1 (FIG. 1) to the gate G2. Now as shown in FIG. 5, a second insulating layer 22 is deposited on the SRAM structure. A second opening is made in layer 22 for the first metal contact plugs. The metal plug is usually formed from a barrier metal such as tungsten. A first metal layer 26 is then deposited and patterned to form the first level of interconnections on the SRAM integrated circuit. Although the metal contact is shown adjacent to the gate G2 contact for clearer visualization, it should be understood that the metal contact plug is formed to any area on the substrate where an electrical contact is required.
There are a number of concerns with the prior art structure and process which degrade the performance and reliability of the SRAM. For example, during the etching of the contact opening 2, photoresist is in direct contact with the gate oxide and can introduce contaminants such as sodium into the oxide resulting in unstable device properties. And still another serious problem is the P.sup.+ /N.sup.+ junction formed by the stacked contact between the doped polysilicon layers 14 and 18 in the contact opening 2. Although the dopant concentrations are high, the junctions still have diode characteristic which reduce the on current (I.sub.on) when the SRAM cell is switches to the opposite state. Ideally, one would prefer a low resistance ohmic stacked contact.
Therefore, there is a strong need in the semiconductor industry for improved structures and processes for making thin film transistors for SRAMs and other integrate circuits that do not have the above problems, and is cost effective.